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cy62147ev30 mobl ? automotive 4-mbit (256k x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-66256 rev. ** revised january 31, 2011 features very high speed: 45 ns temperature ranges ? automotive-a: ?40 c to +85 c ? automotive-e: ?40 c to +125 c wide voltage range: 2.20 v to 3.60 v pin compatible with cy62147dv30 ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 7 ? a (automotive-a) ultra low active power ? typical active current: 2 ma (automotive-a) at f = 1 mhz easy memory expansion with ce [1] and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 48-ball very fine ball grid array (vfbga) (single/dual ce option) and 44-pin thin small outline package (tsop) ii packages byte power-down feature functional description the cy62147ev30 is a high performance cmos static ram (sram) organized as 256k words by 16 bits. this device features advanced circuit desi gn to provide ultra low active current. it is ideal for provid ing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99 percent when deselected (ce high or both ble and bhe are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: deselected (ce high) outputs are disabled (oe high) both byte high enable and byte low enable are disabled (bhe , ble high) write operation is active (ce low and we low) to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 10 for a complete description of read and write modes. for best practice recommendati ons, refer to the cypress application note an1064, sram system guidelines . note 1. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 256k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce [1] we bhe a 16 a 0 a 1 a 9 a 10 ble a 17 bhe ble ce power down circuit logic block diagram [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 2 of 15 contents product portfolio .............................................................. 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 4 thermal resistance........................................................... 5 data retention characteristics ....................................... 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 11 ordering code definitions ..... .................................... 11 package diagrams .......................................................... 12 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 3 of 15 pin configuration figure 1. 48-ball vfbga (single chip enable) [3, 4] figure 2. 48-ball vfbga (dual chip enable) [3, 4] figure 3. 44-pin tsop ii [3] product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62147ev30ll auto-a 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7 auto-e 2.2 3.0 3.6 55 ns 2 3 15 25 1 20 we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe nc a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss a 17 we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe ce 2 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss a 17 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 15 a 16 a 8 a 9 a 10 a 11 a 13 a 14 a 12 oe bhe ble ce we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss nc 10 a 17 notes 2. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 3. nc pins are not connected on the die. 4. pins h1, g2, and h6 in the bga package are address expansion pins for 8 mb, 16 mb, and 32 mb, respectively. [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 4 of 15 maximum ratings exceeding the maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied ......................................... ?55 c to + 125 c supply voltage to ground potential .......................... ?0.3 v to + 3.9 v (v ccmax + 0.3 v) dc voltage applied to outputs in high z state [5, 6] .............. ?0.3 v to 3.9 v (v ccmax + 0.3 v) dc input voltage [5, 6 ] ........... ?0.3 v to 3.9 v (v ccmax + 0.3 v) output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >2001 v (mil-std-883, method 3015) latch up current....................................................... >200 ma operating range device range ambient temperature v cc [7] cy62147ev30ll auto-a ?40 c to +85 c 2.2 v to 3.6 v auto-e ?40 c to +125 c electrical characteristics over the operating range parameter description test conditions 45 ns (auto-a) 55 ns (auto-e) unit min typ [8] max min typ [8] max v oh output high voltage i oh = ?0.1 ma 2.0 ? ? 2.0 ? ? v i oh = ?1.0 ma, v cc > 2.70 v 2.4 ? ? 2.4 ? ? v v ol output low voltage i ol = 0.1 ma ? ? 0.4 ? ? 0.4 v i ol = 2.1 ma, v cc = 2.70 v ? ? 0.4 ? ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc + 0.3 1.8 ? v cc + 0.3 v v cc = 2.7 v to 3.6 v 2.2 ? v cc + 0.3 2.2 ? v cc + 0.3 v v il input low voltage v cc = 2.2 v to 2.7 v ?0.3 ? 0.6 ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v ?0.3 ? 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ?4 ? +4 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ?4 ? +4 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ?1520 ?1525ma f = 1 mhz ? 2 2.5 ? 2 3 i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2 v v in > v cc ? 0.2 v, v in < 0.2 v f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = 3.60 v ?1 7 ?120 ? a i sb2 [9] automatic ce power-down current ? cmos inputs ce > v cc ? 0.2 v v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.60 v ?1 7 ?120 ? a capacitance for all packages. [10] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 5. v il(min) = ?2.0 v for pulse durations less than 20 ns. 6. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 7. full device ac operation assumes a minimum of 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 8. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 9. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 10. tested initially and after any design or proce ss changes that may affect these parameters. [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 5 of 15 thermal resistance [13] parameter description test conditions vfbga package tsop ii package unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 75 77 ? c / w ? jc thermal resistance (junction to case) 10 13 ? c / w figure 4. ac test load and waveforms parameters 2.50 v 3.0 v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics over the operating range parameter description conditions min typ [11] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [12] data retention current v cc = 1.5 v, ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v auto-a ? 0.8 7 ? a auto-e ? ? 12 t cdr [13] chip deselect to data retention time 0 ? ? ns t r [14] operation recovery time cy62147ev30ll-45 45 ? ? ns cy62147ev30ll-55 55 ? ? figure 5. data retention waveform [15, 16] v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v all input pulses r th r1 equivalent to: thevenin equivalent v cc(min) v cc(min) t cdr v dr > 1.5v data retention mode t r v cc ce or bhe .ble notes 11. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 12. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 13. tested initially and after any design or proce ss changes that may affect these parameters. 14. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 15. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 16. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling the chip enable signals or by disabling both bhe and ble . [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 6 of 15 switching characteristics over the operating range parameter [17, 18] description 45 ns (auto-a) 55 ns (auto-e) unit min max min max read cycle t rc read cycle time 45 ? 55 ? ns t aa address to data valid ? 45 ? 55 ns t oha data hold from address change 10 ? 10 ? ns t ace ce low to data valid ? 45 ? 55 ns t doe oe low to data valid ? 22 ? 25 ns t lzoe oe low to low z [19] 5?5?ns t hzoe oe high to high z [19, 20] ?18?20ns t lzce ce low to low z [19] 10 ? 10 ? ns t hzce ce high to high z [19, 20] ?18?20ns t pu ce low to power-up 0 ? 0 ? ns t pd ce high to power-down ? 45 ? 55 ns t dbe ble /bhe low to data valid ? 45 ? 55 ns t lzbe ble /bhe low to low z [19] 10 ? 10 ? ns t hzbe ble /bhe high to high z [19, 20] ?18?20ns write cycle [21] t wc write cycle time 45 ? 55 ? ns t sce ce low to write end 35 ? 40 ? ns t aw address setup to write end 35 ? 40 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 35 ? 40 ? ns t bw ble /bhe low to write end 35 ? 40 ? ns t sd data setup to write end 25 ? 25 ? ns t hd data hold from write end 0 ? 0 ns t hzwe we low to high z [19, 20] ?18?20ns t lzwe we high to low z [19] 10 ? 10 ? ns notes 17. test conditions for all parameters other than tri-state parame ters assume signal transition time of 3 ns (1v/ns) or less, ti ming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ac test load and waveforms on page 5 . 18. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 19. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 20. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 21. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble , or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write. [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 7 of 15 switching waveforms figure 6. read cycle no. 1 address transition controlled [22, 23] figure 7. read cycle no. 2: oe controlled [23, 24, 25] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes 22. the device is continuously selected. oe , ce = v il , bhe , ble , or both = v il . 23. we is high for read cycle. 24. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 25. address valid before or similar to ce and bhe , ble transition low. [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 8 of 15 figure 8. write cycle no. 1: we controlled [26, 27, 28, 29] figure 9. write cycle no. 2: ce controlled [26, 27, 28, 29] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 30 t bw t sce data i/o address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data i/o oe bhe /ble note 30 notes 26. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 27. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble , or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by goi ng inactive. the data input setup and hold timing must be referenced to the edge o f the signal that terminates the write. 28. data i/o is high impedance if oe = v ih . 29. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 30. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 9 of 15 figure 10. write cycle no. 3: we controlled, oe low [31, 32] figure 11. write cycle no. 4: bhe /ble controlled, oe low [31, 32] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 33 ce address we data i/o bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 33 data i/o address ce we bhe /ble notes 31. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 32. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 33. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 10 of 15 truth table ce [34, 35] we oe bhe ble i/os mode power h x x x x high z deselect/power-down standby (i sb ) l x x h h high z deselect/power-down standby (i sb ) l h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h l h l data out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) notes 34. bga packaged device is offered in single ce and dual ce options. in this data sheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. 35. for the dual chip enable device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels is not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 11 of 15 ordering information speed (ns) ordering code package diagram package type operating range 45 cy62147ev30ll-45bvxa 51-85150 48-ball very fine pitch ball grid array (pb-free) [36] automotive-a CY62147EV30LL-45B2XA 51-85150 48-ball very fine pitch ball grid array (pb-free) [37] cy62147ev30ll-45zsxa 51-85087 44-pin thin small outline package ii (pb-free) 55 cy62147ev30ll-55zsxe 51-85087 44-pin thin small outline package ii (pb-free) automotive-e contact your local cypress sales repres entative for availability of these parts. ordering code definitions temperature range: a = auto motive-a, e = automotive-e package type: zsx = tsop ii (pb- free), bvx = vfbga (pb-free) etc. xx = speed grade 45 /55 ns low power voltage range (3v typical) e = process technology 90 nm buswidth = 16 density = 4-mbit family code: mobl sram family company id: cy = cypress cy xx xxx 621 4 7 e v30 ll x notes 36. this bga package is offered with single chip enable. 37. this bga package is offered with dual chip enable. [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 12 of 15 package diagrams figure 12. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 51-85150 *f 51-85150 *f [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 13 of 15 acronyms document conventions units of measure figure 13. 44-pin tsop ii, 51-85087 package diagrams (continued) 51-85087 *c acronym description cmos complementary metal oxide semiconductor i/o input/output sram static random access memory vfbga very fine ball grid array tsop thin small outline package symbol unit of measure c degrees celsius ? a microamperes ma milliampere mhz megahertz ns nanoseconds pf picofarads v volts ? ohms w watts [+] feedback
cy62147ev30 mobl ? document number: 001-66256 rev. ** page 14 of 15 document history page document title: cy62147ev30 mobl ? automotive 4-mbit (256k x 16) static ram document number: 001-66256 rev. ecn no. orig. of change submission date description of change ** 3123973 rame 01/31/2011 created new datasheet for au tomotive parts from document number 38-05440 rev. *i [+] feedback
document number: 001-66256 rev. ** revised january 31, 2011 page 15 of 15 mobl is a registered trademark, and more battery life is a trademark of cypress semiconductor. all product and company names me ntioned in this document are the tr ademarks of their respective holders. cy62147ev30 mobl ? ? cypress semiconductor corporation, 2011. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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